Computer systems typically use inexpensive and high density dynamic random access memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). As JEDEC has promulgated new DDR standards, there have been significant periods in which multiple generations of DDR DRAMs, such as DDR3 and DDR4, are popular. In addition, JEDEC specifies another class of DRAM that is designed specifically for the needs of modern graphics processors, known as graphics DDR (gDDR) memory, and one generation, gDDR5, remains popular today. Thus, it is important for memory controllers to be able to flexibly interface to any one of these plus potentially other emerging memory types.
Memory controller flexibility is also important for the memory system to meet the needs of the different types of products that use it. For example, memories are typically designed with a power-of-two density to simplify layout and decoding. Memory chip densities have historically increased exponentially as modern integrated circuit lithography techniques have evolved. Thus historically DRAM sizes have evolved from 64 kilobit (64 Kb) available in the mid 1980s, to 128 Kb, to 256 Kb, and so on until the present in which DDR DRAMs are commonly available in 4-, 8-, and 16-gigabit (Gb) densities. There are two reasons why this trend may not continue. First, semiconductor lithography technology may be approaching physical limits. Thus memory manufacturers may offer intermediate sizes that are not power-of-two. Second, designers may need memory having densities that are not close to the nearest power of two size, and may not want the extra product cost that comes with the next higher density. Thus memory manufacturers have started designing non power-of-two memory sizes to better meet these realities. Interfacing to non power-of-two memories places additional burdens on memory controller manufacturers to design the circuitry that meets all possible configurations without excessive cost.
Memory systems operate more efficiently if the memory controller is able to access different banks in an interleaved fashion without causing page conflicts. By interleaving accesses to different banks, the memory controller is able to partially hide the overhead that would be required for a series of accesses to different rows in the same bank. Known memory controllers use a circuit that scrambles or “swizzles” the input address so that sequential accesses to the same rank and bank will be spread across multiple banks. For example, the memory controller uses certain address bits to scramble the bank address so that memory accesses in a relatively small region of the address space are mapped to different banks. The bank scramble algorithm implemented by this memory controller provides a pattern of accesses with a desirable level of interleaving for some systems but not for others, depending on the type of system, the characteristics of the accesses generated by the application program and the operating system, etc.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.